The present invention relates to a favorable motion image compression system used when motion image data are compressed and transmitted.
FIG. 1 is a block diagram showing the configuration of a conventional motion image data compression system that processes motion images as units of N frames (where, in this example, N=4).
Five frames of digitally connected image data from the 0th frame (F.sub.0) to the 4th frame (F.sub.4) from a circuit (not indicated in the figure) are respectively stored in frame memories 1 through 5 (refer to FIG. 2). A motion vector detection circuit 6 divides the data of frame I (I=1, 2, 3) into blocks B.sub.I for each 8.times.8 pixels for example, and each block B.sub.I units has the motion vector MV0I between frame F.sub.0 and frame F.sub.I and the motion vector MV4I between frame F.sub.4 and frame F.sub.I calculated and output to a motion compensation predictor circuit 7.
The motion compensation predictor circuit 7 uses the motion vectors MV0I and MV4I as the reference for performing motion compensation predictive for the block B.sub.I for a required mode, and the prediction error signals are output to a predictive error signal coding circuit 10 via a switch 8. In addition, the motion compensation predictor circuit 7 outputs data relating to the motion vector and the predictive mode to the predictive error signal coding circuit 10. The predictive error signal coding circuit 10 codes the data that is read from the input frame F.sub.2 via the switch 8, and codes the predictive error signals output from the predictive compensation predictor circuit 7. In addition, the/a motion vector mode coding circuit 9 codes the motion vector and the predictive mode. A microprocessor 11 overlaps the output of the predictive error signal coding circuit 10 and the motion vector mode coding circuit 9, and outputs it to a demodulation system via a transmission system not indicated in the figure.
The motion compensation predictor circuit 7 is configured as indicated in FIG. 3 for example.
An address generating circuit 21 generates an address of block B.sub.0 from an address of block B.sub.I input by an address generating circuit 23 and the motion vector MV0I for between frames F.sub.0 and F.sub.I, reads the data of that address from frame memory 1, and stores it in a work memory 24. In the same manner, an address generating circuit 22 generates an address of block B.sub.4 from the address of the block B.sub.I input from the address generating circuit 23 and the motion vector MV4I for between frames F.sub.4 and F.sub.I, reads that address from the frame memory 2 and stores it in the work memory 25.
During this time, the number of blocks is counted by a block counter 29.
The data of block B.sub.0 that is written to the work memory 24 is input to the mode judgment circuit 28 and also supplied to an adder 27. In the same manner, the data of block B.sub.4 that is written to a mode judgment circuit 28 is input to the mode judgment circuit 28 and also supplied to the adder 27. The adder 27 multiplies the data of block B.sub.0 input from the work memory 24, by a coefficient (1-.omega.) (where .omega.=I/4), and the data for block B.sub.4 input from a work memory 25 is multiplied by the coefficient .omega. and the two are added.
More specifically, the adder 27 outputs the block B.sub.04 by linear interpolation of blocks B.sub.0 and B.sub.4, as shown by the following equation. EQU B.sub.04 =B.sub.0 .times.w+B4.times.(1-W)
The data of this block B.sub.04 is also output to the mode judging circuit 28.
During this time, the number of pixels is counted by a pixel counter 30.
In addition, the address generating circuit 23 reads the address of block B.sub.I from one of the frame memories 3 through 5 and outputs it to a work memory 26. The data of block B.sub.I that is stored in the work memory 26 is supplied to the mode judging circuit 28.
The mode judging circuit 28 is configured as shown in FIG. 4, for example.
The data of the block B.sub.I that is stored in the work memory 26 is supplied to correlation calculation circuits 41 through 44, and to the direct current (DC) component calculation circuit 45. The DC component calculation circuit 45 averages the data of block B.sub.I, generates a block B.sub.DC and outputs it to the correlation calculation circuit 44. The data of blocks B.sub.0, B.sub.4 and B.sub.04 are input to correlation calculation circuits 41 through 43.
The correlation calculation circuit 41 calculates the correlation between blocks B.sub.0 and B.sub.I and the mean square error (MSE0) between the two and outputs them. In the same manner, the correlation calculation circuit 42 calculates the correlation between blocks B.sub.4 and B.sub.I and the mean square error (MSE4) between the two and outputs them, the correlation calculation circuit 43 calculates the correlation between blocks B.sub.04 and B.sub.I and the mean square error (MSE04) between the two and outputs them, and the correlation calculation circuit 44 calculates the correlation between blocks B.sub.DC and B.sub.I and the mean square error (MSEDC) between the two and outputs them. Then, the respective coefficient values SEL0, SEL4, SEL04 and SELDC are determined as follows.
SEL0=MSE0 PA0 SEL4=MSE4 PA0 SEL04=MSE04 PA0 SELDC=MSEDC.times..alpha.+.beta. PA0 0&lt;.alpha.&lt;1 PA0 0&lt;.beta.
Where .alpha. and .beta. are coefficients the satisfy the following conditions.
These correlation values becomes smaller when the correlation with block B.sub.I becomes higher.
A minimum value judgment circuit 46 judges the smallest value from the four correlation values, and makes the corresponding mode the predication mode. Then, that predictive mode and the motion vector in that predictive mode is output to the motion vector coding circuit 9 and a predictive error signal corresponding to the difference between the block B.sub.I and a constant value and the blocks B.sub.0, B.sub.4, B.sub.04 predicted in the predictive mode is generated and output to the predictive error signal coding circuit 10.
More specifically, each of the modes can be described in the following manner.
Mode 1: Block B.sub.0 is the predictive block and the motion vector MV0I is coded.
Mode 2: Block B.sub.4 is the predictive block and the motion vector MV4I is coded.
Mode 3: Block B.sub.04 is the predictive block and the motion vectors MV0I and MV4I are coded.
Mode 4: Block B.sub.DC is the predictive block and the motion vector is not coded.
In this manner, in the conventional apparatus, when mode 3 is selected, coding is performed for the two motion vectors MV0I and MV4I and there is the problem that the amount of coding becomes large.
In addition, when there is movement of one pixel in four frames, there is a minute movement of one pixel or less between frames. However, it is not possible to predict movement of one pixel or less and so since there is no method for the expression of movement in units of one pixel, the error between the predicted pixel and the actual pixel becomes large. Accordingly, the amount of coding of the predictive error block corresponding to the predictive error signal becomes large.